The present disclosure relates to methods for electrochemically depositing a conductive material, for example, a metal, such as copper (Cu), cobalt (Co), nickel (Ni) gold (Au), silver (Ag), manganese (Mn), tin (Sn), aluminum (Al), and alloys thereof, in features (such as trenches and vias, particularly in Damascene applications) of a microelectronic workpiece.
An integrated circuit is an interconnected ensemble of devices formed within a semiconductor material and within a dielectric material that overlies a surface of the semiconductor material. Devices which may be formed within the semiconductor include MOS transistors, bipolar transistors, diodes, and diffused resistors. Devices which may be formed within the dielectric include thin film resistors and capacitors. The devices are interconnected by conductor paths formed within the dielectric. Typically, two or more levels of conductor paths, with successive levels separated by a dielectric layer, are employed as interconnections. In current practice, copper and silicon oxide are commonly used for, respectively, the conductor and the dielectric.
The deposits in a copper interconnect typically include a dielectric layer, a barrier layer, a seed layer, copper fill, and a copper cap. Because copper tends to diffuse into the dielectric material, barrier layers are used to isolate the copper deposit from the dielectric material. However, for other metal interconnects besides copper, it should be appreciated that barrier layers may not be required. Barrier layers are typically made of refractory metals or refractory compounds, for example, titanium (Ti), tantalum (Ta), titanium nitride (TiN), tantalum nitride (TaN), etc. Other suitable barrier layer materials may include manganese (Mn) and manganese nitride (MnN). The barrier layer is typically formed using a deposition technique called physical vapor deposition (PVD), but may also be formed by using other deposition techniques, such as chemical vapor deposition (CVD) or atomic layer deposition (ALD).
A seed layer may be deposited on the barrier layer. However, it should also be appreciated that direct on barrier (DOB) deposition is also within the scope of the present disclosure, for example, barriers that are made from alloys or co-deposited metals upon which interconnect metals may be deposited without requiring a separate seed layer, such as titanium ruthenium (TiRu), tantalum ruthenium (TaRu), tungsten ruthenium (WRu), as well as other barrier layers that are known and/or used by those having skill in the art.
In one non-limiting example, the seed layer may be a copper seed layer. As another non-limiting example, the seed layer may be a copper alloy seed layer, such as copper manganese, copper cobalt, or copper nickel alloys. In the case of depositing copper in a feature, there are several exemplary options for the seed layer. First, the seed layer may be a PVD copper seed layer. See, e.g., FIG. 3 for an illustration of a process including PVD copper seed deposition. The seed layer may also be formed by using other deposition techniques, such as CVD or ALD.
Second, the seed layer may be a stack film, for example, a liner layer and a PVD seed layer. A liner layer is a material used in between a barrier and a PVD seed to mitigate discontinuous seed issues and improve adhesion of the PVD seed. Liners are typically noble metals such as ruthenium (Ru), platinum (Pt), palladium (Pd), and osmium (Os), but the list may also include cobalt (Co) and nickel (Ni). Currently, CVD Ru and CVD Co are common liners; however, liner layers may also be formed by using other deposition techniques, such as ALD or PVD.
Third, the seed layer may be a secondary seed layer. A secondary seed layer is similar to a liner layer in that it is typically formed from noble metals such as Ru, Pt, Pd, and Os, but the list may also include Co and Ni, and most commonly CVD Ru and CVD Co. (Like seed and liner layers, secondary seed layers may also be formed by using other deposition techniques, such as ALD or PVD.) The difference is that the secondary seed layer serves as the seed layer, whereas the liner layer is an intermediate layer between the barrier layer and the PVD seed. See, e.g., FIGS. 5 and 6 for illustrations of processes including secondary seed depositions, followed by, respectively, ECD seed deposition in FIG. 5, as described below, and flash deposition in FIG. 6. (A “flash” deposition is primarily on the field and at the bottom of the feature, without significant deposition on the sidewalls of the feature.)
After a seed layer has been deposited according to one of the examples described above, the feature may include a seed layer enhancement (SLE) layer, which is a thin layer of deposited metal, for example, copper having a thickness of about 2 nm. An SLE layer is also known as an electrochemically deposited seed (or ECD seed). See, e.g., FIG. 4 for an illustration of a process including PVD seed deposition and ECD seed deposition. See, e.g., FIG. 5 for an illustration of a process including secondary seed deposition and ECD seed deposition. As seen in FIGS. 4 and 5, ECD seed may be a conformally deposited layer.
An ECD copper seed is typically deposited using a basic chemistry that includes a very dilute copper ethylenediamine (EDA) complex. ECD copper seed may also be deposited using other copper complexes, such as citrate, tartrate, urea, etc., and may be deposited in a pH range of about 2 to about 11, about 3 to about 10, or in a pH range of about 4 to about 10.
After a seed layer has been deposited according to one of the examples described above (which may also include an optional ECD seed), conventional ECD fill and cap may be performed in the feature, for example, using an acid deposition chemistry. Conventional ECD copper acid chemistry may include, for example, copper sulfate, sulfuric acid, methane sulfonic acid, hydrochloric acid, and organic additives (such as accelerators, suppressors, and levelers). Electrochemical deposition of copper has been found to be the most cost effective manner by which to deposit a copper metallization layer. In addition to being economically viable, ECD deposition techniques provide a substantially bottom up (e.g., nonconformal) metal fill that is mechanically and electrically suitable for interconnect structures.
Conventional ECD fill, particularly in small features, may result in a lower quality interconnect. For example, conventional ECD copper fill may produce voids, particularly in features having a size of less than 30 nm. As one example of a type of void formed using conventional ECD deposition, the opening of the feature may pinch off. Other types of voids can also result from using the conventional ECD copper fill process in a small feature. Such voids and other intrinsic properties of a deposit formed using conventional ECD copper fill can increase the resistance of the interconnect, thereby slowing down the electrical performance of the device and deteriorating the reliability of the copper interconnect.
Therefore, there exists a need for an improved, substantially void-free metal fill process for a feature. Such substantially void-free metal fill may be useful in a small feature, for example, a feature having an opening size of less than 30 nm.